Solid-state image sensors in general comprise photodetector means for detecting radiation from an image and converting the radiation to charge carriers, and transfer means for carrying the charge carriers to an output circuit. In one type of solid-state image sensor, an interline area sensor, the CCD imager includes a plurality of photodetectors, or pixels, disposed in an array of rows and columns, with CCD shift registers arranged between the rows of the photodetectors. The photodetectors in each row are coupled by transfer gates to their adjacent CCD shift registers so that the charge carriers accumulated in the photodetectors can periodically be transferred to the CCD shift registers. In another type of sensor, a full frame sensor, a charge-coupled device (CCD) is employed as both photodetector and transfer means. A single CCD shift register at the bottom of the sensor transfers the charge carriers to an on-chip amplifier for read-out. Full frame sensors require a mechanical shutter.
In a full frame CCD sensor, a pixel typically comprises two phases, each phase being provided with a gate and each including a storage region and a barrier region. The minimum gate voltage typically required to be applied in the vertical clocks to cause majority carrier (hole) accumulation at the Si/SiO.sub.2 interface in the storage regions of the pixels is between -6.5 and -7.5 volts; this voltage is referred to as the accumulation potential. Application of the accumulation potential to the gates of the sensor suppresses the dark current generated at the semiconductor-dielectric interface. Vertical clock voltages are generally set to operate between -8 and +0.5 volts, this latter voltage being briefly applied to transfer charges between phases. Generation of a -8 volt clock voltage requires a -15 volt power supply.